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Part: PHD95N03LT
Category:
Discrete
-> Transistors
-> FETs (Field Effect Transistors)
-> MOSFETs
-> Power MOSFETs
-> N-Channel
Description: PHD95N03LT; Trenchmos (tm) Logic Level Fet
Company: Philips Semiconductors
Datasheet :
download File size : 89 kB
Datasheet text preview:
PHD95N03LT
TrenchMOSTM logic level FET
Rev. 02 -- 8 February 2002
M3D300
Product data
1. Description
N-channel logic level field-effect power transistor in a plastic package using TrenchMOSTM1 technology. Product availability: PHD95N03LT in SOT428 (D-PAK).
2. Features
s Low on-state resistance s Fast switching.
3. Applications
s High frequency computer motherboard DC to DC converters.
4. Pinning information
Table 1: Pin 1 2 3 mb Pinning - SOT428, simplified outline and symbol Description gate (g) drain (d) source (s) mounting base, connected to drain (d)
2 1 Top view 3
MBK091
Simplified outline
[1]
Symbol
d
mb
g s
MBB076
SOT428 (D-PAK)
[1] It is not possible to make connection to pin 2 of the SOT428 package.
1.
TrenchMOS is a trademark of Koninklijke Philips Electronics N.V..
Philips Semiconductors
PHD95N03LT
TrenchMOSTM logic level FET
5. Quick reference data
Table 2: VDS ID Ptot Tj RDSon Quick reference data Conditions Tj = 25 to 175 °C Tmb = 25 °C; VGS = 5 V Tmb = 25 °C VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A Typ 5 7.5 Max 25 75 115 175 7 9 Unit V A W °C m m drain-source voltage (DC) drain current (DC) total power dissipation junction temperature drain-source on-state resistance Symbol Parameter
6. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR ID VGS IDM Ptot Tstg Tj IS ISM EAS drain-source voltage (DC) drain-gate voltage (DC) drain current (DC) gate-source voltage peak drain current total power dissipation storage temperature operating junction temperature source (diode forward) current (DC) Tmb = 25 °C peak source (diode forward) current Tmb = 25 °C; pulsed; tp 10

s non-repetitive avalanche energy unclamped inductive load; ID = 75 A; tp = 0.1 ms; VDD = 15 V; RGS = 50 ; VGS = 5V; starting Tj = 25 °C unclamped inductive load; VDD = 15 V; RGS = 50 ; VGS = 5V; star ting Tj = 25 °C Tmb = 25 °C; pulsed; tp 10

s; Figure 3 Tmb = 25 °C; Figure 1 Conditions Tj = 25 to 175 °C Tj = 25 to 175 °C; RGS = 20 k Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 Tmb = 100 °C; VGS = 5 V; Figure 2 Min -55 -55 Max 25 25 75 61

20 240 115 +175 +175 75 240 120 Unit V V A A V A W °C °C A A mJ
Source-drain diode
Avalanche ruggedness
IAS
non-repetitive avalanche current
-
75
A
9397 750 09286
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 -- 8 February 2002
2 of 12
Philips Semiconductors
PHD95N03LT
TrenchMOSTM logic level FET
03aa16
03ae86
120
Pder
120 Ider (%) 80
(%)
80
40
40
0 0 50 100 150 200 o Tmb ( C)
0 0 50 100 150 200 Tmb (ºC)
Pt o t P d e r = ---------------------- × 100 % P °
t o t ( 25 C )
ID I d e r = ------------------- × 100 % I °
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of mounting base temperature.
Fig 2. Normalized continuous drain current as a function of mounting base temperature.
103
03ae87
ID (A)
RDSon = VDS / ID
tp = 10

s 100

s
102
1 ms DC 10 ms 100 ms
10
1 1 10 VDS (V) 102
Tmb = 25 °C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09286
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 -- 8 February 2002
3 of 12