الرجاء مساعدتى فى هده التصميم .مهم للامتحانى
Design the circuit that functions is described below and test its working on DE2 FPGA board.
There is a clock circuit consist of three State machines.
First and second state machine is used for both second and minute counting. It counts till 60 and generate Cout signal at the and of counting.
Thirt state machine is used for clock counting. It counts till 24 and generate Cout signal at the and of counting.
There must ve two 7 segment connection at each state machine to Show counting.
The clock pulse frequency must be 1 Hz. To optain this frequency you have to use exra counter with Cout signal ant it must count till 1.000.000. Because our FPGA boards’ internal clock generator is 50 MHZ
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