8255 PPI:
The 8255 Programmable Parallel Interface is used extensively in the computer
industry as a means to access the 'outside world'.
Primarily it consists of three 8-bit ports (A,B, and C) which can be programmed
individually to function as an input or an output port. The pin outs for this
40-pin device are as follows:
D7 - D0 Bi-directional Data Bus
Reset Reset input. (the 3 ports are set to input in mode 0)
CS Chip Select input (active low)
RD Read input (active low)
WR Write input (active low)
A0 - A1 Port address input (these are normally connected to the
CPU address lines A0 and A1 thus providing 4
consecutive addresses to address the 8255)
PA7 - PA0 Port A 8 bits (input/output)
PB7 - PB0 Port B 8 bits (input/output)
PC7 - PC0 Port C 8 bits (input/output)
Vcc +5 volts
GND 0 volts
With A0A1 = 00 data can be read/written from/to port A
With A0A1 = 01 data can be read/written from/to port B
With A0A1 = 10 data can be read/written from/to port C
In order to be able to program the 8255 there is a special register (whose
address is obtained by setting A0 and A1 to 1) in the PPI which has to be
initialised to the required values according to the table given below. This
is known as the control word and has to be output to the PPI before actually
using the PPI. It should be noted that you can only write to the control
register. With a single control word, the operation of all the three ports
can be set up.
Each port can be programmed in any one of three modes:
Mode 0: simple input or output ports
Mode 1: Input or output port with handshaking
Mode 2: A bi-directional i/o port with 5 handshaking lines
The control word can be made up as shown:
D7 1 Signifies mode setting
D6 D5 00 Group A mode 0
01 Group A mode 1
1X Group A mode 2
D4 1 Port A (Group A) input
0 Port A (Group A) output
D3 1 Port C upper 4 bits (Group A) input
0 Port C upper 4 bits (Group A) output
D2 0 Group B mode 0
1 Group B mode 1
D1 1 Port B (Group B) input
0 Port B (Group B) output
D0 1 Port C lower 4 bits (Group B) input
0 Port C lower 4 bits (Group B) output
When D7 is set to 0, the Control Word signifies a bit set/reset operation,
which allows individual bits of port C only, to be set or reset.In this case
the control word would be as shown:
D7 0 Port C bit set/reset operation
D6D5D4 XXX Don't care bits (can have any value)
D3D2D1 Can very from 000 to 111 to indicate which bit out of 8
D0 0 Bit set to 1
1 Bit reset to 0
This bit set/reset function is used extensively in mode 1 and mode 2 in order
to enable the interrupt outputs.
MODE 0: This is a simple straight forward input or output operation and no
special knowledge is required in order to be able to use the 8255 in this mode.
This mode is useful for i/o devices that do not need special synchronisation
pulses to exchange data with the CPU, such as keyboard interfacing.
MODE 1: Strobed I/O
In this mode port A and/or Port B are programmed as data ports and port C is
programmed to carry the status or control signals. There are 4 possible
configurations for the 8255 in this mode corresponding to the 4 combinations
of operating the ports as either input or output.
INPUT MODE 1
When a group is placed into mode 1 input, the functional layout is indicated
by the figure shown. As can be seen, an input port in this mode has two status
lines that interface to the device the 8255 in controlling. These lines are the
STB (STROBE) and IBF (INPUT BUFFER FULL). The STB line is an input to the 8255
used by the device to gate information into the 8255 input port. The IBF signal
should be monitored by the device attached to the 8255. When high, the device
should refrain from strobing information into the 8255. If the IBF signal is
ignored, the old information will be overwritten by the new information.
The third status line is an INTR (INTERRUPT REQUEST) output that interfaces to
the CPU. Upon receipt of data into a port, the 8255 can generate an interrrupt
request if the INTE (INTERRUPT ENABLE) mask bit is set high. If this mask bit
is set low, the INTR output line is prevented from going high.
Mode 1 operation is sometimes referred to as as status-driven, because data
transfers will not take place unless the logic levels of the status lines are
correct. This means that data transfers are conditional. In contrast, mode 0
uses unconditional data transfers. In conditional data transfers, the status
lines provide handshaking signals that allow the 8255 to talk to the device it
is controlling and allow the 8255 to talk to the CPU.
A typical input data transfer begins with the device checking the status of
the IBF line. If this line is high, the device will refrain from placing new
information for the 8255. Once this line is sensed at a low logic level, the
device connected to the 8255 will strobe information into the port by pulling
the STB line low. At this time, the information is gated (or latched) into the
port. Once this happens, the IBF signal goes high, preventing further data
transfers. If the INTE mask bit is set, the 8255 will generate an INTR signal.
Once this INTR signal is accepted by the CPU at its INT pin, an Interrupt
Service Routine (ISR) is called to read the data. When the RD line of the 8255
is accesed, the data is transferred into the CPU, IBF goes low, and the INTR
request from the 8255 is cleared. The device senses IBF going low, which will
allow to transfer another byte of data, thus repeating the process.
In order to set or reset the mask bit, a set/reset control word (with D7 set
to 0 ),is sent to the 8255 via the control port. The pin location accessed is
PC4 for group A and PC2 for group B. These mask bits occupy the logical
positions indicated and are electrically isolated form the STB function. This
means that it is not possible to determine the status of the mask bit by
sensing the logic level of the STB input pins. To determine the status of these
bits, a status read operation must be performed.
OUTPUT mode 1:
The figure below shows the functional layout of the ports when they are
configured as output ports. Two new status lines are now in use. Those are the
OBF ( OUTPUT BUFFER FULL ) and the ACK (ACKNOWLEDGE ). In a typical polled
output sequence, the CPU monitors the status of OBF. If OBF is low, the output
port contains valid information that has not yet been gated to the device. So
when OBF is low, the CPU will refrain from sending additional information.
When the device is ready to accept information, it checks OBF. If it is low,
the device generates a low-level ACK pulse. This pulse gates information into
the device and sets OBF high. The next time the CPU polls the OBF status bit,
it detects a high, and transfers the next byte.
In an output situation using interupts, the CPU must enable INTR by setting the
mask bit. These bits are PC6 for group A and PC2 for group B. As before, they
are electrically isolated from the pins, which this time are used for the ACK
function.
Once the mask is set, the CPU must transfer the first byte to start the cycle.
When the first byte is transferred, the OBF goes low. This is sensed by the
device, which, when ready, generates an ACK. The ACK going low transfers the
information to the device and sends OBF back high. When OBF goes high, an INTR
is generated. This request causes the CPU to execute a service routine that
sends another byte of information, repeating the process.
The status register layout is shown in figure below. It is possible to mix
modes and input/output configuration. Port A can be mode 1 input while port B
is mode 1 output or even mode 0 input or output. To obtain the status
information, the CPU must perform an RD from port C. Finally, two port C pins
are available for I/O; these are either PC6/7 or PC4/5 depending on the
configuration programmed. When used as outputs, these lines are set or cleared
using the set/reset control word. When used as inputs, the logic levels can be
monitored from the status register.
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ربــــــــط Ppi بالـــــ 8086
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