//   DC V 500           //

     //    ENG ABDALLA  HYGAZY    //
    //    DATA  2020/12/19         //
    //    Frequency  4  MHz       //
    
    #define  seg_data1   PORTB
    #define  seg_data2   PORTB
    #define  seg_data3   PORTB
    #define  seg_data4   PORTB
    #define  DP         PORTB.f7
    #define  BUZ      PORTA.F5=1;  delay_ms(250);  PORTA.F5=0;  delay_ms(80);
    #define  DDS4    delay_ms(2000);
    #define  DDS5    delay_ms(800);
  

  
   //********************========************************//
     unsigned int adc_rd,DATA,DATA_X,STOP=0,NEXT;
     unsigned int DATA_LOW,DATA_MEDEM,DATA_HAY;
     unsigned int RD_DATA=0,RD_DATA1=0,RD_DATA2=0;
     unsigned int AA1=0,AA2,AA3,AA4=0,AA5=0,AA6=0 ;
     long tlong;
     unsigned short mask(unsigned short num);
     unsigned int  a1=0,m1=0,e1=0,w1=0,k1=0;
  //********************========************************//

  //======================= show_adc ==========================================//
      void show_adc() {
      adc_rd = ADC_Read(0);
      tlong = (long)adc_rd * 500000;
     tlong = tlong / 1023;
 }
  //=============== show_adc === END ========================================//
 
 

  
  //============ Timer0 =========== InitTimer0 ========================//
    //Timer0
   //Prescaler 1:8; TMR0 Preload = 6; Actual Interrupt Time : 1 ms
   //Place/Copy this part in declaration section
   void InitTimer0(){
   OPTION_REG         = 0x82;
   TMR0                 = 6;
   INTCON         = 0xA0;
 }
 //========================      END    ===============================//
 
 //========================  Interrupt ===============================//
    void Interrupt(){
    if (TMR0IF_bit){
    TMR0IF_bit         = 0;
    TMR0         = 6;
    //Enter your code here
    
         AA4++;  AA5++; AA6++;
         if( AA4==1 ) { show_adc(); }
         if( AA4==1000 ) { AA4=0;   }


      if(STOP==0)
    {
    
       if(AA5==1)
      {
       a1 = tlong / 100000;
      if(a1==0){ PORTD=0;}
      else  PORTD=1;

       PORTB=mask(a1); a1=0;

      }
      
      if(AA5==2)
      {
       a1 = (tlong % 100000)/10000;
       PORTD=2;
       PORTB=mask(a1);  a1=0;

      }

      if(AA5==3)
      {
       a1   = (tlong % 10000)%1000/100;
       PORTD=4;
       PORTB=mask(a1); a1=0;

     }
     
     

      if(AA5==5)
      {
       a1  = (tlong % 100)%10%1;   //////////
       PORTD=4;
       PORTB=mask(10);

      }
     
     
     
     
      if(AA5==6)
      {
       a1  = (tlong % 100)%10%1;
       PORTD=8;
       PORTB=mask(a1); a1=0;

      }
      
      if(AA5==7){ AA5=0;}
     
  }
         if(AA6==1   ){ PORTD.F7=1;}
         if(AA6==400 ){ PORTD.F7=0;}
         if(AA6==800){ AA6=0;     }
    

  }
}

 //===================  Interrupt == END  ===============================//
 

 
 //========================   void main  ==========================//
   
      void main() {
      TRISB=0;  PORTB=0;
      TRISD=0;  PORTD=0;
      TRISC=0;  PORTC=0;
      TRISE=0;  PORTE=0;
      TRISA=1;  PORTA=0;
      ADCON0=0x00;
      CMCON=0;
      InitTimer0();

      RD_DATA  = EEPROM_Read(0); delay_ms(10);
      RD_DATA  = RD_DATA  *10;
      
      RD_DATA1 = EEPROM_Read(1); delay_ms(10);
      RD_DATA1 = RD_DATA1 *10;
       
      RD_DATA2 = EEPROM_Read(2); delay_ms(10);
      RD_DATA2 = RD_DATA2 *10;

      delay_ms(1000);
      BUZ   BUZ

        
       if( tlong <=15 )
       { 
        
            while(AA1==0)
          {
           delay_ms(3000);  BUZ   
           if( tlong >=15 ){ AA1=1;  }
          }
      }
        

       
       
      while(1){









 }
}

 //====================== void main === END  ==========================//
 
 
 //========================   switch (num)  ==========================//
unsigned short mask(unsigned short num){
switch (num){

case 0 : return 0xC0;
case 1 : return 0xF9;
case 2 : return 0xA4;
case 3 : return 0xB0;
case 4 : return 0x99;
case 5 : return 0x92;
case 6 : return 0x82;
case 7 : return 0xF8;
case 8 : return 0x80;
case 9 : return 0x90;
case 10 : return 0x7F;

}
}

//========================      END    ==========================//